The present invention relates generally to Hall effect devices and more particularly to an improved Hall effect device that is integratable on a semiconductor chip.
The Hall effect is based on the fact that a charge moving in a magnetic field experiences a Lorentz force proportional to the magnitudes of the applied current and magnetic field. If a metal or semiconductor material carrying a current is placed in an orthogonal magnetic field, an electric field is induced within the material in a direction which is mutually perpendicular to both the current and the magnetic field. The Lorentz force tends to cause the current carriers, i.e., electrons or holes, to accumulate closer to one surface of the material. Since equilibrium must be maintained within the system there is also a charge generated by the accumulated static field which equals the Lorentz force. Therefore a potential difference, the Hall voltage, appears between opposite surfaces of the material.
The use of the Hall effect in semiconductor integrated circuits for linear and switching applications is well known in the art. Practical Hall devices must exhibit high sensitivity, wide operating temperature range, insensitivity to mechanical stress, and durability. Improvements in silicon technology have made it possible to overcome the low mobility and poor sensitivity of silicon by fabricating circuits in which Hall effect generators, preamplifiers, signal conditioning circuits and trigger circuits are integrated on the same semiconductor chip. See, for example, U.S. Pat. No. 4,141,026 to Bate et al., entitled "Hall Effect Generator".
The topology of a typical Hall element structure is shown in FIG. 1, wherein the silicon Hall generator 10 is formed of an N-type epitaxial region 12 surrounded by a P+-type isolation region 14. An insulating layer such as silicon dioxide overlying regions 12 and 14 has openings therein to allow conductors to contact N+-type regions formed in the surface of region 12. The conductors form the current, or force, terminals 16, 18 and the voltage sense terminals 20, 22 of the Hall device. With no magnetic field applied the Hall device 10 can be modeled as a resistor bridge as shown in FIG. 2. In an ideal device R1=R2 and R3=R4, which results in an offset voltage V.sub.os =V.sub.2 -V.sub.1 =0.
Variations in the potential on the surface of the silicon dioxide layer will induce variations in the resistance of the underlying silicon. For example, a negative surface potential that is less than the flatband voltage will deplete the N-type silicon surface resulting in a reduction in the thickness of the neutral region in the epitaxial layer, thereby locally increasing the resistance. Conversely, a surface potential greater than the flatband voltage will accumulate the underlying silicon surface resulting in a localized reduction in resistance due to increased conductivity. These resistance changes directly affect the offset voltage.
The offset voltage in prior devices varies unpredictably from device to device and is sensitive to mechanical stress. Further, temperature-induced stress is a problem, particularly with plastic encapsulated devices. Linear Hall effect integrated circuits typically exhibit an output drift equivalent to an input of 4-10 gauss per degree C. These offset voltage instabilities severely limit the usefulness of semiconductor Hall effect devices.